`include "defines.v"
`timescale 1ns / 1ns
module if_(
    input wire rst,
    //from pc_reg
    input wire[`InstAddrBus] InstAddr_i,
    //from inst_ram
    input wire[`InstBus] Inst_i,

    //to id
    output reg[`InstBus] Inst_o,
    //to inst_ram and id
    output reg[`InstAddrBus] InstAddr_o

);

always @ (*) 
    begin
        if (rst == `RstEnable)
            begin
                InstAddr_o = `ZeroWord;
                Inst_o = `ZeroWord;
            end
        else
            begin
                InstAddr_o = InstAddr_i;
                Inst_o = Inst_i; 
            end
    end
endmodule
